1. Field of the Invention
The present invention relates to flash memory control, and more particularly, to a method for managing a memory apparatus, and an associated memory apparatus thereof.
2. Description of the Prior Art
While a host is accessing a memory apparatus (e.g. a solid state drive, SSD), the host typically sends an accessing command and at least a corresponding logical address to the memory apparatus. The controller of the memory apparatus receives the logical address and transfers the logical address into a physical address by utilizing a logical-to-physical address linking table. Thus, the controller accesses at least one physical memory element (or memory component) of the memory apparatus by utilizing the physical address. For example, the memory element can be implemented with one or more flash memory chips (which can be referred to as flash chips for simplicity).
The logical-to-physical address linking table can be built in accordance with a memory unit in the memory element. For example, the logical-to-physical address linking table can be built by blocks or by pages. When the logical-to-physical address linking table is built by blocks, the logical-to-physical address linking table can be referred to as the logical-to-physical block address linking table. When the logical-to-physical address linking table is built by pages, the logical-to-physical address linking table can be referred to as the logical-to-physical page address linking table. In addition, a logical-to-physical page address linking table comprising linking relationships about pages of a plurality of blocks (or all blocks) in the memory apparatus can be referred to as the global page address linking table.
Assume that the memory element has X physical blocks, and each physical block has Y physical pages. In a situation where the logical-to-physical address linking table is built by blocks, the associated logical-to-physical block address linking table can be built by reading a logical block address stored in a page of each physical block and recording the relationship between the physical block and the associated logical block. In order to build the logical-to-physical block address linking table, X pages respectively corresponding to the X physical blocks have to be read, where the time required for this is assumed to be x seconds.
In a situation where the logical-to-physical address linking table is built by pages, the associated global page address linking table can be built by reading a logical page address stored in each physical page of all physical blocks and recording the relationship between the physical page and the associated logical page. In order to build the global page address linking table, at least X·Y pages have to be read, requiring x·Y seconds. If a block has 1024 pages, the time required for building the global page address linking table is 1024 times the time required for building the logical-to-physical block address linking table, i.e. 1024·x seconds, which is an unacceptable processing time since the processing speed is too slow. That is, when implementing the global page address linking table in this way, the overall performance of accessing the memory apparatus is retarded. Therefore, a novel method is required for efficiently building the logical-to-physical address linking table, and related methods for managing memory apparatus operated under the novel method is required.